The present invention relates to low power integrated circuit designs and, more particularly to recycling power in an integrated circuit.
Integrated circuits include numerous semiconductor devices, which are connected together and powered through a plurality of conductive xe2x80x9cnetsxe2x80x9d. Several of these nets, such as clock lines, have a tendency to repetitively switch between logic high and logic low states during normal operation of the integrated circuit. In certain applications, up to 30% of the power consumed by an integrated circuit is used for charging and discharging these repetitively switching nets.
It is desirable for integrated circuits to consume as little power as possible, particularly for power sensitive circuits such as portable electronic devices. Typical approaches to reducing power consumption in an integrated circuit include lowering supply voltages, the use of low leakage transistors, and turning off unused portions of the integrated circuit. However even with these approaches, a large amount of power will still be consumed nets that are repetitively charged and discharged. Improved power savings approaches are therefore desired which are capable of recycling at least some of this lost power.
One embodiment of the present invention is directed to an integrated circuit clock network, which includes at least one clock net, including a first clock net, a clock driver, and a switched capacitor network. The clock driver has a clock output coupled to the first clock net. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the clock network, selectively coupled to the first clock net in parallel with one another, and selectively coupled to at least one of the clock nets in series with one another.
Another embodiment of the present invention is directed to an integrated circuit. The integrated circuit includes a plurality of nets and a switched capacitor network. The plurality of nets includes a first logic net having a tendency to repetitively switch between logic high and low states during normal operation of the integrated circuit. The switched capacitor network includes a plurality of capacitors, which are selectively decoupled from the plurality of nets, selectively coupled to the first logic net in parallel with one another, and selectively coupled to at least one of the nets in series with one another.
Yet another embodiment of the present invention is directed to a method of recycling power in an integrated circuit having a plurality of nets. The method includes: (a) repetitively switching a first of the nets on the integrated circuit between logic high and low states during normal operation of the integrated circuit; (b) temporarily coupling a plurality of capacitors to the first net in parallel with one another when the first net is in the logic high state and then decoupling the plurality of capacitors from the first net while the first net is still in the logic high state; and (c) temporarily coupling the plurality of capacitors in series with one another to at least one of the nets, after step (b).